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NXP Semiconductors /MIMXRT1052 /USDHC1 /INT_STATUS_EN

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Interpret as INT_STATUS_EN

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CCSEN_0)CCSEN 0 (TCSEN_0)TCSEN 0 (BGESEN_0)BGESEN 0 (DINTSEN_0)DINTSEN 0 (BWRSEN_0)BWRSEN 0 (BRRSEN_0)BRRSEN 0 (CINSSEN_0)CINSSEN 0 (CRMSEN_0)CRMSEN 0 (CINTSEN_0)CINTSEN 0 (RTESEN_0)RTESEN 0 (TPSEN_0)TPSEN 0 (CTOESEN_0)CTOESEN 0 (CCESEN_0)CCESEN 0 (CEBESEN_0)CEBESEN 0 (CIESEN_0)CIESEN 0 (DTOESEN_0)DTOESEN 0 (DCESEN_0)DCESEN 0 (DEBESEN_0)DEBESEN 0 (AC12ESEN_0)AC12ESEN 0 (TNESEN_0)TNESEN 0 (DMAESEN_0)DMAESEN

DTOESEN=DTOESEN_0, CEBESEN=CEBESEN_0, BGESEN=BGESEN_0, DCESEN=DCESEN_0, DINTSEN=DINTSEN_0, TCSEN=TCSEN_0, DEBESEN=DEBESEN_0, TPSEN=TPSEN_0, CINSSEN=CINSSEN_0, AC12ESEN=AC12ESEN_0, DMAESEN=DMAESEN_0, CCESEN=CCESEN_0, BRRSEN=BRRSEN_0, CRMSEN=CRMSEN_0, BWRSEN=BWRSEN_0, CCSEN=CCSEN_0, TNESEN=TNESEN_0, CIESEN=CIESEN_0, CINTSEN=CINTSEN_0, CTOESEN=CTOESEN_0, RTESEN=RTESEN_0

Description

Interrupt Status Enable

Fields

CCSEN

Command Complete Status Enable

0 (CCSEN_0): Masked

1 (CCSEN_1): Enabled
TCSEN

Transfer Complete Status Enable

0 (TCSEN_0): Masked

1 (TCSEN_1): Enabled
BGESEN

Block Gap Event Status Enable

0 (BGESEN_0): Masked

1 (BGESEN_1): Enabled
DINTSEN

DMA Interrupt Status Enable

0 (DINTSEN_0): Masked

1 (DINTSEN_1): Enabled
BWRSEN

Buffer Write Ready Status Enable

0 (BWRSEN_0): Masked

1 (BWRSEN_1): Enabled
BRRSEN

Buffer Read Ready Status Enable

0 (BRRSEN_0): Masked

1 (BRRSEN_1): Enabled
CINSSEN

Card Insertion Status Enable

0 (CINSSEN_0): Masked

1 (CINSSEN_1): Enabled
CRMSEN

Card Removal Status Enable

0 (CRMSEN_0): Masked

1 (CRMSEN_1): Enabled
CINTSEN

Card Interrupt Status Enable

0 (CINTSEN_0): Masked

1 (CINTSEN_1): Enabled
RTESEN

Re-Tuning Event Status Enable

0 (RTESEN_0): Masked

1 (RTESEN_1): Enabled
TPSEN

Tuning Pass Status Enable

0 (TPSEN_0): Masked

1 (TPSEN_1): Enabled
CTOESEN

Command Timeout Error Status Enable

0 (CTOESEN_0): Masked

1 (CTOESEN_1): Enabled
CCESEN

Command CRC Error Status Enable

0 (CCESEN_0): Masked

1 (CCESEN_1): Enabled
CEBESEN

Command End Bit Error Status Enable

0 (CEBESEN_0): Masked

1 (CEBESEN_1): Enabled
CIESEN

Command Index Error Status Enable

0 (CIESEN_0): Masked

1 (CIESEN_1): Enabled
DTOESEN

Data Timeout Error Status Enable

0 (DTOESEN_0): Masked

1 (DTOESEN_1): Enabled
DCESEN

Data CRC Error Status Enable

0 (DCESEN_0): Masked

1 (DCESEN_1): Enabled
DEBESEN

Data End Bit Error Status Enable

0 (DEBESEN_0): Masked

1 (DEBESEN_1): Enabled
AC12ESEN

Auto CMD12 Error Status Enable

0 (AC12ESEN_0): Masked

1 (AC12ESEN_1): Enabled
TNESEN

Tuning Error Status Enable

0 (TNESEN_0): Masked

1 (TNESEN_1): Enabled
DMAESEN

DMA Error Status Enable

0 (DMAESEN_0): Masked

1 (DMAESEN_1): Enabled

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data